hdl-registers 6.0.1

Description:

hdlregisters 6.0.1

The hdl-registers project is an open-source HDL register interface code generator fast enough to run
in real time.
It makes FPGA/ASIC development more fun by automating a lot of time-consuming manual work.
It also minimizes the risk of bugs by removing the need for duplicate information.
Read more
See documentation on the website: https://hdl-registers.com
Check out the source code on GitHub: https://github.com/hdl-registers/hdl-registers
The following features are supported:

Register fields

Bit.
Signed/unsigned fixed-point bit vector.
Enumeration.
Positive/negative-range integer.


Register arrays.
Default registers.
Register constants.

Registers can be defined using
a TOML/JSON/YAML data file
or the Python API.
The following code can be generated:

VHDL

AXI-Lite register file wrapper using records and native VHDL types for values.
Simulation support packages for compact read/write/wait/checking of register and field values.


C++

Complete class with setters and getters for registers and fields.
Includes an abstract interface header for unit test mocking.


C header
with register addresses and field information.
HTML
website with documentation of registers and fields.
Python
class with methods to read/write/print each register and field on a target device.

The tool can also be extended by
writing your own code generator
using a simple but powerful API.
This project is mature and used in many production environments.
The maintainers place high focus on quality, with everything having good unit test coverage and a
thought-out structure.